Flip Flop

SR Flip-Flop
JK Flip-Flop
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Introduction - Basic Flip-Flop Circuit

The memory elements in a sequential circuit are called flip-flops . A flip-flop circuit has two outputs , one for the normal value and one for the complement value of the stored bit . Binary information can enter a flip-flop in a variety of ways and gives rise to different types of flip-flops. A flip-flop circuit can be constructed from two NAND gates or two NOR gates . These flip-flops are shown in Figure 1 and Figure 2 . Each flip-flop has two outputs, Q and Q', and two inputs, set and reset . This type of flip-flop is referred to as an SR flip-flop or SR latch . The flip-flop in Figure 1 has two useful states. When Q = 1 and Q' = 0, it is in the set state (or 1-state). When Q=0 and Q'=1, it is in the clear state (or 0-state). The outputs Q and Q' are complements of each other and are referred to as the normal and complement outputs, respectively. The binary state of the flip-flop is taken to be the value of the normal output.

When a 1 is applied to both the set and reset inputs of the flip-flop in Figure 1, both Q and Q' outputs go to 0. This condition violates the fact that both outputs are complements of each other. In normal operation this condition must be avoided by making sure that 1's are not applied to both inputs simultaneously.

(a) Logic diagram

(b) Truth table

Figure 1. Basic flip-flop circuit with NOR gates

(a) Logic diagram

(b) Truth table

Figure 2. Basic flip-flop circuit with NAND gates

Clocked SR Flip-Flop

The clocked SR flip-flop shown in Figure 3 consists of a basic NOR flip-flop and two AND gates . The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0 , regardless of the S and R input values. When the clock pulse goes to 1 , information from the S and R inputs passes through to the basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0. When the pulse is removed, the state of the flip-flop is indeterminate, ie., either state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse.

(a) Logic diagram

(c) Truth table

Figure 3. Clocked SR flip-flop

(b) Graphical symbol

Timing diagram

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Clocked JK Flip-Flop

A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q = 1 , it switches to Q = 0 and vice versa.

A clocked JK flip-flop is shown in Figure 4 . Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.

Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this, the clock pulses must have a time duration less than the propagation delay through the flip-flop.

(a) Logic diagram

(c) Graphical Symbol

Figure 4. Clocked JK flip-flop

(b) Transition Table

Timing diagram

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